![]() The setup check is violated, the data will not be captured at the next clock edge The hold requirement for the next flop for same clock edge has been met so thatĪs said earlier, setup and hold timings are to be met in order to ensure thatĭata launched from one flop is captured properly at the next flop at next clockĮdge so as to transfer the state-machine of the design to the next state. Similarly, hold check ensures that data is stable until Setup check ensures that the data is stableīefore the setup requirement of next active clock edge at the next flop so that These conditions areĮnsured by setup and hold checks. Should not be captured at next flop at the same edge. ![]() So, data launched at one edge should beĬaptured at next active clock edge. State machines), the next state is derived from its previous state. Considering the way digital designs of today are designed (finite Timing checks ensure that a data launched from one flop is captured at another Setup and hold checks in a design : Basically, setup and hold In other words, hold time can be termed as delay taken by data from ‘Node A’ to ‘Node C’. Similarly, it is necessary to ensure a stable value at the input to ensure a stable value at ‘ Node C’. ![]() If that is not the case, it will be accounted for accordingly). This time for data to reach from ‘Node A’ to ‘Node F’ is termed as data setup time (assuming CLK and CLK' are present instantaneously. Since, data has to travel ‘NodeA’ -> ‘Node B’ -> ‘Node C’ -> ‘Node D’ -> ‘Node E’ -> ‘Node F’ to reach ‘Node F’, it should arrive at flip-flop’s input (Node A) at some earlier time. For data to be latched by ‘latch 1’ at the falling edge of the clock, it must be present at ‘Node F’ at that time. Now, let us get into the details of above figure. Just inverting the transmission gates’ clock, we get negative-level sensitive D-type latch. Figure below shows a positive-level sensitive D-type latch. A D-type latch, in turn, is realized using transmission gates and inverters. A D-type flip-flop is realized using two D-type latches one of them is positive level-sensitive, the other is negative level-sensitive. Let us discuss the origin of setup time and hold time taking an example of D-flip-flop as in VLSI designs, D-type flip-flops are almost always used. It is very important to understand the origin of setup time and hold time as whole design functionality is ensured by these. If even a single flop exists that does not meet setup and hold requirements for timing paths starting from/ending at it, the design will fail and meta-stability will occur. Rightly so, for the chip to function properly, setup and hold timing constraints need to be met properly for each and every flip-flop in the design. Cause/origin of setup time and hold time : Setup time and hold time are said to be the backbone of timing analysis.
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